Basic and Advanced Design and Layout Techniques
By Keith Armstrong. First published February 2007
Perfect bound (with titled spine):   ISBN 978-0-9555118-1-3
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This book is for electronic circuit designers, as well as for PCB designers themselves, and has full-colour figures throughout.

All application areas are covered, from household appliances, commercial, industrial and medical equipment, through automotive to aerospace and military.

The techniques it describes save time and cost whilst reducing financial risks and improving performance. They help you to… 

  • Improve signal integrity (SI), signal/noise ratio (S/N), especially in mixed technologies
  • Comply with EMC Directive, FCC, etc. with the lowest cost of manufacture
  • Reduce the number of iterations of hardware and software to reduce time-to-market whilst also reducing financial risks
  • Improve the reception range of co-located wireless voice or data communications
    (GSM, PCS, GPRS, EDGE, CDMA2000, UMTS, Bluetooth, Wi-Fi, UWB, etc.)
  • Improve GPS or Galileo reception when using co-located antennas
  • Save cost, size and weight by reducing (or eliminating) shielding and filtering of the overall enclosure
  • Improve reliability and reduce warranty costs without adding significantly to the cost of manufacture
  • Use very high-speed devices, high-power digital signal processing (DSP), the latest IC technologies (90 or 65nm), and/or the latest packaging technologies (e.g. chip scale, flip-chip, micro-BGA, etc.) 

The eight chapters cover…

1)     Saving time and cost overall

2)     Segregation and interface suppression

3)     PCB-chassis bonding

4)     Reference planes for 0V and power

5)     Decoupling, including buried capacitance technology

6)     Transmission lines (and any traces carrying high-speed signals or noise)

7)     Routing and layer stacking, including microvia technology

8)    A number of miscellaneous issues (heatsinks, in-circuit testing, etc.)

This book describes the techniques, and when they are appropriate, in practical engineering language. It does not describe why they work in great detail, and only uses a few simple maths formulas where they are practically useful.

However, these techniques are very well proven in practice and the reasons why they work are well understood. The many web-based references lead to detailed explanations and mathematical foundations.

It is difficult for textbooks to keep up to date with PCB technology and EMC techniques, which is why most of the references are conference papers and articles written during the last few years.

Although the subject is EMC, many of the techniques are essential for achieving good SI or S/N and such issues are often discussed – especially in the few areas where EMC and SI requirements could conflict.

Complete list of contents

Chapter 1 Saving Time and Cost Overall

1.1 Reasons for using these EMC techniques

1.1.1                Development – reducing costs and getting to market on time
1.1.2                Reducing unit manufacturing costs
1.1.3                Enabling wireless datacommunications
1.1.4                Enabling the use of the latest ICs and IC packages
1.1.5                Easier compliance for high-power DSP
1.1.6                Improving the immunity of analogue circuits

1.2 What do we mean by “high speed”

1.3 Electronic trends, and their implications for PCBs

1.3.1                Shrinking silicon
1.3.2                Shrinking packaging              
1.3.3                Shrinking supply voltages              
1.3.4                PCBs are becoming as important as hardware and software              
1.3.5                EMC testing trends              
1.3.6                Frequency, velocity and wavelength

1.4 Designing to reduce project risk

1.4.1                Guidelines, maths formulae, and field solvers
1.4.2                Virtual design
1.4.3                Experimental verification

1.5 Responsibility for EMC

1.6 EMC-competent QA, change control, cost-reduction

1.7 Compromises

Chapter 2 Segregation and Interface Suppression

2.1 The Basics of Segregation and Interface Suppression

2.1.1                Segregating the ‘Inside World’ from the ‘Outside World’
2.1.2                Segregation inside the Inside World
2.1.3                Implementing segregation on a PCB
2.1.4                Interface suppression
2.1.5                Implementing interface suppression on a PCB
2.1.6                The synergy of shielding and filtering

2.2 PCB-level shielding

2.2.1                Reasons for shielding on the PCB
2.2.2                Overview of shielding at PCB level
2.2.3                Types of PCB shielding-can
2.2.4                Attaching shielding-cans to PCBs
2.2.5                PCB shielding-can materials
2.2.6                Apertures and gaps in shielding-cans
2.2.7                Waveguide-below-cutoff methods
2.2.8                Near field effects on shielding
2.2.9                Cavity resonances

2.3 Interconnections and shielding

2.3.1                Combining PCB shielding with filtering

2.4 Combining shielding with heatsinking

2.5 Environmental issues

2.6 PCB-level filtering

2.6.1                Reasons for filtering on the PCB
2.6.2                Overview of PCB filtering
2.6.3                High-performance filtering requires a good quality RF reference
2.6.4                Design of single-stage low-power and signal PCB filters
2.6.5                Power filtering on PCBs
2.6.6                Filtering for shielded connectors

2.7 Placement of off-board interconnections

Chapter 3 PCB-to-Chassis Bonding

3.1 Introduction to PCB-to-chassis bonding

3.1.1                What do we mean by ‘chassis’?
3.1.2                What do we mean by ‘bonding’?
3.1.3                Hybrid bonding
3.1.4                ‘Ground loops’ and religion

3.2 Why bond PCB 0V planes to chassis anyway?

3.2.1                Reduced transfer impedance
3.2.2                Better control of common-mode ‘leakage’

3.3 Benefits of closer spacing between a PCB and its chassis

3.4 The ‘highest frequency of concern’

3.5  Controlling resonances in the PCB-chassis cavity

3.5.1                Why and how the cavity resonates
3.5.2                Wavelength rules
3.5.3                Increasing the number of bonds to increase resonant frequencies
3.5.4                What if we can’t use enough bonds?
3.5.5                Spreading the resonances more widely to reduce peak amplitude
3.5.6                Designing resonances to miss problem frequencies
3.5.7                Being clever with capacitors
3.5.8                Using resistors to ‘dampen’ cavity resonances
3.5.9                Using absorber to ‘dampen’ cavity resonances
3.5.10              Reducing the impedance of capacitive bonds
3.5.11              Using shielding techniques
3.5.12              Using fully shielded PCB assemblies

3.6 Daughter and mezzanine boards

Chapter 4 Reference Planes for 0V and Power

4.1 Introduction to Reference Planes

4.2 Design issues for reference planes

4.2.1                Plane dimensions
4.2.2                Dealing with gaps and holes in planes
4.2.3                Cross-hatching and copper fills
4.2.4                Connecting devices to planes
4.2.5                Thermal breaks
4.2.6                Device placement
4.2.7                Fills and meshes
4.2.8                Resonances in the 0V plane
4.2.9                Cavity resonances in plane pairs
4.2.10              Reducing the ‘edge-fired’ emissions from plane pairs
4.2.11              Locating via holes for aggressive signals or power
4.2.12              When traces change layers
4.2.13              Component-side planes for DC/DC converters and clocks

4.3 Splitting a 0V plane is not generally a good idea any more

4.4 When traces must cross a 0V or power plane split

4.5 Advantages of ‘High Density Interconnect’ (HDI), ‘build-up’ and ‘microvia’ PCB technologies

4.6 The totally shielded PCB assembly

Chapter 5 Decoupling, including Buried Capacitance Technology

5.1 Introduction to decoupling

5.2 Decoupling with discrete capacitors

5.2.1               Which circuit locations need decaps?
5.2.2               The benefits of decaps in ICs and MCMs
5.2.3               How much decoupling capacitance to use?
5.2.4               Types of decaps
5.2.5               Layouts that reduce the size of the current loop
5.2.6               Series resonances in decaps
5.2.7               Using ferrites in decoupling
5.2.8               Splitting the decap into two
5.2.9               Using multiple decaps in parallel
5.2.10             Other ways to reduce decap ESL

5.3 Decoupling with 0V/Power plane pairs

5.3.1               Introduction to the decoupling benefits of 0V/Power plane pairs
5.3.2               The distributed capacitance of a 0V/Power plane pair
5.3.3               PCB 0V and power routing with 0V/Power plane pairs
5.3.4               Location of decaps
5.3.5               Defeating parallel decap resonances when using 0V/Power plane pairs
5.3.6               ‘Cavity resonances’ in 0V/Power plane pairs
5.3.7               Bonding planes with decaps to increase resonant frequencies
5.3.8               Power plane islands fed by π filters
5.3.9               Damping cavity resonance peaks
5.3.10             The spreading inductance of planes
5.3.11             The 20-H rule
5.3.12             Taking advantage of decap series resonances
5.3.13             Decap walls
5.3.14             Other 0V/Power plane pair techniques to reduce emissions
5.3.15             The buried capacitance technique

5.4 Field solvers for power bus impedance simulations

Chapter 6   Transmission lines (and any traces carrying high-speed signals or noises)

6.1 Matched transmission lines on PCBs

6.1.1               Introduction
6.1.2               Propagation velocity, V and characteristic impedance, Z0
6.1.3               The effects of impedance discontinuities
6.1.4               The effects of keeping Z0 constant
6.1.5               Time Domain Reflectometry (TDR)
6.1.6               When to use matched transmission lines
6.1.7               Increasing importance of matched transmission lines for modern products
6.1.8               It is the real rise/fall times that matter
6.1.9               Noises and immunity should also be taken into account
6.1.10             Calculating the waveforms at each end of a trace
6.1.11             Examples of two common types of transmission lines
6.1.12             Coplanar transmission lines
6.1.13             The effects of capacitive loading
6.1.14             The need for PCB test traces
6.1.15             The relationship between rise/fall-time and frequency

6.2 Terminating transmission lines

6.2.1               A range of termination methods
6.2.2               Difficulties with drivers
6.2.3               Compromises in line matching
6.2.4              ICs with ‘smart’ terminators
6.2.5               Bi-directional terminations
6.2.6               Non-linear termination techniques
6.2.7               ‘Equalising’ terminations
6.2.8               Location of terminations at the ends of transmission-lines

6.3 Transmission line routing constraints

6.3.1               General routing guidelines
6.3.2               A transmission line exiting a product via a cable
6.3.3               Interconnections between PCBs inside a product
6.3.4               Changing plane layers within one PCB
6.3.5               Crossing plane breaks or gaps within one PCB
6.3.6               Avoid sharp corners in traces
6.3.7               Linking return current planes with vias or decaps
6.3.8               Effects of via stubs
6.3.9               Effects of routing around via fields
6.3.10             Other effects of the PCB stack-up and routing
6.3.11             Some issues with microstrip

6.4 Differential matched transmission lines

6.4.1               Introduction to differential signalling
6.4.2               CM and DM characteristic impedances in differential lines
6.4.3               Exiting PCBs, or crossing plane splits with differential lines
6.4.4               Controlling imbalance in differential signalling
6.4.5               Routing asymmetry

6.5 Choosing a dielectric

6.5.1               Effects of woven substrates (like FR4 and G-10)
6.5.2               Other types of PCB dielectrics

6.6 Matched-impedance connectors

6.7 Shielded PCB transmission lines

6.7.1               ‘Channelised’ striplines
6.7.2               Creating fully shielded transmission lines inside a PCB

6.8 Miscellaneous related issues

6.8.1               Impedance matching, transforming and AC coupling
6.8.2               A ‘safety margin’ is a good idea
6.8.3              Filtering
6.8.4               CM chokes
6.8.5               Replacing parallel busses with serial
6.8.6               The lossiness of FR4 and copper
6.8.7               Problems with coated microstrip
6.8.8               The effects of bond-wires and leads

6.9   Simulators and solvers help design matched transmission lines

6.10 Some useful sources of further information on PCB transmission lines

Chapter 7 Routing and Layer Stacking, including Microvia Technology

7.1 Routing and layer stacking techniques, and microvia technology

7.2 Routing

7.3 Stack-ups

7.3.1               The benefits of closer trace-plane spacing
7.3.2               The benefits of closer component-plane spacing
7.3.3               Copper balancing
7.3.4               Single-layer PCBs
7.3.5               Two-layer PCBs
7.3.6               Four-layer PCB stack-ups
7.3.7               Six layer PCBs
7.3.8               Eight layer PCBs
7.3.9               PCBs with more than eight layers
7.3.10             Number of PCB layers and cost-effective design in real-life
7.3.11             Shielding power planes with different voltages

7.4 EMC issues with copper balancing using area fills or cross-hatches

7.5 HDI PCB technology

7.5.1               What is HDI?
7.5.2               The EMC benefits of HDI
7.5.3               HDI suppliers and costs
7.5.4               HDI PCD design issues
7.5.5               More information on HDI

7.6 Current capacity of traces

7.6.1               Handling surge and transient currents
7.6.2               Maximum continuous DC and low frequency current handling
7.6.3               Voltage drops in the PCB’s power distribution
7.6.4               Handling continuous RF currents
7.6.5               A note on accuracy

7.7 Transient and surge voltage capacity of layouts

7.7.1               Trace-trace and trace-metal spacing
7.7.2               The EMC and safety problems caused by compliance with the RoHS directive

Chapter 8    A Number of Miscellaneous Final Issues

8.1 Power supply connections to PCBs

8.2 Low-K dielectrics

8.3 Chip-scale packages (CSPs)

8.4 Chip-on-board (COB)

8.5 Heatsinks on PCBs

8.5.1               EMC effects of heat sinks
8.5.2               Heat sink RF resonances
8.5.3               Bonding heatsinks to a PCB plane
8.5.4               Combining shielding with heatsinking
8.5.5               Other heatsink techniques that may help
8.5.6               Heatsinks for power devices

8.6 Package resonances

8.7  Eliminate the test pads for bed-of-nails or flying probe testing

8.8 Unused I/O pins

8.9 Crystals and oscillators

8.10  IC tricks

8.11 Location of terminations at the ends of transmission-lines

8.12 Electromagnetic Band Gap (EBG)

8.13 Some final PCB design issues

8.14 Beware board manufacturers changing layouts or stack-ups

8.15 Future-proofing the EMC design

8.15.1               Marking EMC design features or critical parts on the design drawings
8.15.2               A quality-controlled procedure for EMC design

Glossary of Terms and Abbreviations
Author, Keith Armstrong’s biography